1. Related Applications
This application is related to copending application Ser. No. 08/570,035 filed on Dec. 11, 1995, assigned to the assignee of the present invention.
2. Field of the Invention
The present invention relates, in general, to programable logic devices including field programable gate arrays (FPGAs), and, more particularly, to an apparatus and method for loading data streams used to program or configure FPGAs and for decreasing the amount of space needed to implement the FPGA control circuitry.
3. Statement of the Problem
Programmable logic devices (PLDs) include programable logic arrays (PLAs), field programmable gate arrays (FPGAs) and the like. In PLDs, configurable interconnects are used to connect logic elements, which may themselves be programmable, to each other and to input and output ports. To implement a desired circuit, PLDs must be given the information as to what connections are to be made and/or what logic is to be implemented by each of the logic elements. This is accomplished by applying a "configuration data stream" which is an ordered data stream in which each bit is represented by a binary value, to "configuration lines" formed on the PLD.
The configuration data stream is used to program individual switches inside the PLD to a desired state (i.e., on or off). These switches can be implemented from SRAM cells that control pass transistors, antifuse connection points, fuse connection points, or any other equivalent switch implementation. The programmed switches are used to control the configurable routing and logic of the PLD. In addition, the switches may form a RAM look-up table in FPGA's to implement combinational logic.
A typical PLD may comprise hundreds of programmable switches to accept and hold the configuration data stream. A continuing trend is to increase the logic capabilities of PLDs thereby increasing the number of programmable switches. Some devices employ thousands and tens of thousands of switches per PLD. These switches logically resemble a large addressable memory system with each switch uniquely identified by a column and row address.
In prior PLDs, all of the switches were arranged as a single array. A long shift register containing one bit for each column of switches in the array was used to hold the configuration data for a particular row. A second long shift register was used to load information as to which row in the array the data in the first shift register was to be loaded. Once both shift registers were loaded, all switches in a selected row could be programmed simultaneously by enabling the data in the first shift register to transfer into the programmable switches of the selected row.
Address lines must extend from the first and second shift registers across the entire array of switches in the prior configuration system. Also, each bit of both of the long shift registers must function or it may be impossible to load configuration data into the PLD. A fault in any of the long address lines could propagate backward or forward to other devices, rendering the entire chip non-functional.
In a high density PLD design it is desirable to minimize the physical space required for the control circuitry used to configure the PLD. By minimizing space required for control circuitry, more programmable elements can be added to the device increasing its functionality. At the same time, it is desirable to maximize the data throughput. In particular, when a device is tested and characterized, it is necessary to apply a wide variety of data streams in order to verify functionality of as many circuits as possible.
One prior solution is to provide a single serial interface to apply configuration data to the array of switches in the PLD. This has the advantage of minimizing the space required because only one serial data line needed to be routed through the device. However, a serial interface is too slow for large PLDs.
A second prior solution is to use a parallel external interface that accepts many lines of configuration data. The parallel configuration data is then converted to serial form within the PLD by a parallel-to-serial converter. This solution increased data throughput, however, increased circuit and interface complexity. Also, some space penalty exists because the parallel-to-serial converter circuitry is formed on the PLD chip.
U.S. Pat. No. 5,394,031 issued to Britton et al. on Feb. 28, 1995 describes a method for decreasing the amount of time required to configure an FPGA by allowing data to be loaded in parallel into a shift register. The shift register is configured to shift multiple bits per clock cycle. This solution is similar to the second solution identified above, but uses the on-chip shift register to perform the parallel to serial conversion.
A need exists for a methodology for reducing the time to configure an FPGA using an apparatus that minimizes the physical space required to implement the methodology.